1. Field of the Invention
The present invention generally relates to the art of electronic data transmission, and more specifically to an arrangement for synchronizing a decoder/de-interleaver.
2. Description of the Related Art
Improvements in digital communications technology have increased the demands on Forward Error Correction (FEC) techniques. For example, compressed video systems require an extremely low Bit-Error Rate (BER) on the order of 1e-12 (one error per 10.sup.12 bits of data). Conventional FEC techniques require high transmitter power and large data overhead to achieve these low BERs.
The "rate" R of the code is defined as the reciprocal of the bandwidth expansion. For example, an R=1/2 code doubles the bandwidth or data rate in the transmission channel. If two individual codes are concatenated (an outer code and an inner code), the overall rate is the product of the two codes.
Another measure of the effectiveness of an error correction technique is the Signal to Noise Ratio (SNR) that is required to obtain the necessary BER at the output of the outer decoder. A low SNR corresponds to a low power requirement for the transmitter, and thereby lower cost. The best codes have a high rate R and a low SNR for a given BER.
The inner codes that are selected usually perform well at low SNR (high channel BER). They can easily push the BER from the range of 1e-2 to the range of 1e-4. However, it is difficult for the inner code alone to reach the 1e-12 BER system requirement.
The outer codes, on the other hand, can easily push the BER from 1e-4 to 1e-12, but usually will not work at low SNR. Hence, the concatenated scheme is highly desirable for systems such as Direct Broadcast Satellite (DBS), and create only a moderate bandwidth expansion.
The above analysis applies only to the assumption that the errors are uncorrelated or randomly distributed. In practical applications, the output of the inner decoder tends to be very bursty. This causes the error pattern to be highly correlated and concentrated only in a small portion of the bit stream. Under these conditions, the outer decoder will not perform effectively.
In order to alleviate this problem, an interleaving/de-interleaving function is added to the system. Interleaving is used in combination with encoding for error correction. An advantageous arrangement, which is applicable to numerous types of burst-error communications channels, generally comprises an interleaver connected between the outer encoder and the inner encoder at the transmitter, and a de-interleaver connected the inner decoder and an outer decoder at the receiver. The interleaver redistributes the data bits or symbols being transmitted over the channel so that the symbols are mutually separated by substantially more than the length of a "typical" burst of errors.
Interleaving effectively makes the channel appear like a random-error channel to a decoder at the receiving end. For some high frequency channels, this technique can improve the performance by one to three orders of magnitude. The concatenation and interleaving of several FEC techniques reduces the power and bandwidth expansion required by a single error correction code to obtain the same low error rate.
A problem has remained in the prior art regarding the synchronization of the de-interleaver and the outer decoder. Although the decoder synchronization pulses are generated in response to synchronization signals in the input data stream, the de-interleaver requires B synchronization pulses for each synchronization pulse applied to the outer decoder, where B is the interleave depth.
In addition, the de-interleaver has a latency of [(B-1).times.N]+C system clock pulses, where N is the interleave block length and C is number of clock pulses corresponding to a small constant time interval that depends on the design of the de-interleaver.
The latency of the de-interleaver would, if no compensation were made, cause the data to reach the outer decoder [(B-1).times.N]+C clock pulse periods after the corresponding data, thereby preventing synchronization from occurring.
A prior art solution is to delay the synchronization pulses by [(B-1).times.N]+C decoder synchronization pulse periods such that the decoder synchronization pulses and data reach the outer decoder in synchronism. Typically, a programmable counter is employed to produce the required delay.
For example, the widely used Zenith VSB system uses the parameters B=26 and N=208. Assuming an 8-bit byte length, the count required to produce the desired delay is [(B-1).times.N.times.8]+C=41,000+C clock pulses.
This counter arrangement is disproportionately large and expensive for many applications. In addition, the counter must be programmed for each combination of B and N, requiring additional configuration circuitry.